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| TH8062 Voltage Regulator with LIN Transceiver Features o o o o o Compatible to LIN Specification 2.0 and SAE J2602 Operating voltage VS = 6 ... 18 V Low standby current consumption of typ. 15 A in sleep mode "noload" current < 200A Linear low drop voltage regulator 5V/70mA 2% Output current limitation LIN-Bus Transceiver Compatible to ISO9141 functions Baud rate up to 20 kBaud Slew rate control for best EME behavior Low slew mode for optimized SAE J2602 transmission High EMI immunity High signal symmetry for using in RC - based slave nodes up to 2% clock tolerance Current limitation Bus input voltages -24V to 30V independent from VBat Wake-up via LIN bus traffic Reset output (default 8ms/4.65V) Reset time adjustable to 4ms, 15ms and 30ms during IC final test Over temperature shutdown Automotive temperature range of -40C to 125C CMOS compatible interface to microcontroller Load dump protected (40V) Small SOIC8 package Pin compatible to the Melexis TH8061 o o o o o o o o Ordering Information Part No. TH8062 KDC AA On Request TH8062 KDC AB TH8062 KDC AC TH8062 KDC AD Temperature Range K (-40 to 125 C) K (-40 to 125 C) K (-40 to 125 C) K (-40 to 125 C) Package DC (SOIC8) DC (SOIC8) DC (SOIC8) DC (SOIC8) Version A A A A POR-Time A (8ms) B (4ms) C (30ms) D (15ms) General Description The TH8062 consists of a low-drop voltage regulator 5V/70mA and a LIN bus transceiver. The LIN transceiver is suitable for LIN bus systems conform to LIN specification revision 2.0 and SAE J2602. The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful and cheap slave nodes in LIN Bus systems. TH8062 - Datasheet 3901008062 Page 1 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Contents 1. 2. Functional Diagram ............................................................................................................................... 4 Electrical Specification.......................................................................................................................... 5 2.1 Operating Conditions ....................................................................................................................................... 5 2.2 Absolute Maximum Ratings ............................................................................................................................. 5 2.3 Static Characteristics ....................................................................................................................................... 6 2.3.1. Voltage Regulator and Reset Unit .......................................................................................................... 6 2.3.2. LIN Bus Interface.................................................................................................................................... 8 2.4 Dynamic Characteristics .................................................................................................................................. 9 2.5 Timing Diagrams ............................................................................................................................................ 11 3. Functional Description ........................................................................................................................ 13 3.1 Operating Modes............................................................................................................................................ 13 3.2 Initialization .................................................................................................................................................... 15 3.3 Wake-Up ........................................................................................................................................................ 15 3.4 VSUP under voltage reset.............................................................................................................................. 16 3.5 Overtemperature Shutdown ........................................................................................................................... 16 3.6 LIN BUS Transceiver ..................................................................................................................................... 17 3.7 Linear Regulator............................................................................................................................................. 20 3.8 RESET ........................................................................................................................................................... 21 3.8.1. Programmability of Power-ON-Reset Delay ......................................................................................... 21 3.9 Mode Input EN ............................................................................................................................................... 22 4. 4.1 4.2 4.3 4.4 4.5 Application Hints ................................................................................................................................. 24 Safe Operating Area ...................................................................................................................................... 24 Low Dropout Regulator .................................................................................................................................. 25 Application Circuitry ....................................................................................................................................... 27 EMI Supressing.............................................................................................................................................. 27 Connection to Flash-MCU .............................................................................................................................. 28 5. Operating during Disturbance............................................................................................................ 29 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Operating without VSUP or GND ................................................................................................................... 29 Short Circuit BUS against VBAT .................................................................................................................... 29 Short Circuit BUS against GND...................................................................................................................... 29 Short Circuit TxD against GND ...................................................................................................................... 29 TxD open ....................................................................................................................................................... 29 Short Circuit VCC against GND ..................................................................................................................... 29 Overload of VCC ............................................................................................................................................ 29 Undervoltage VCC ......................................................................................................................................... 29 Undervoltage VSUP ....................................................................................................................................... 30 Short circuit RxD, RESET against GND or VCC ............................................................................................ 30 6. 7. 8. 8.1 8.2 PIN Description .................................................................................................................................... 31 Mechanical Specification .................................................................................................................... 32 Tape and Reel Specification ............................................................................................................... 33 Tape Specification.......................................................................................................................................... 33 Reel Specification .......................................................................................................................................... 34 9. 9.1 9.2 9.3 ESD/EMC Remarks .............................................................................................................................. 35 General Remarks ........................................................................................................................................... 35 ESD-Test ....................................................................................................................................................... 35 EMC ............................................................................................................................................................... 35 10. 11. 12. Revision History................................................................................................................................... 36 Assembly Information ......................................................................................................................... 37 Disclaimer............................................................................................................................................. 38 TH8062 - Datasheet 3901008062 Page 2 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver List of Figures Figure 1 - Block diagram.......................................................................................................................... 4 Figure 2 - Timing diagram for propagation delays................................................................................. 11 Figure 3 - Timing diagram for duty cycle acc. to LIN 2.0 and J2602..................................................... 11 Figure 4 - Timing Diagram for EN mode selection ................................................................................ 12 Figure 5 - State diagram of operating modes........................................................................................ 13 Figure 6 - Operating of power-on and under-voltage reset ................................................................... 15 Figure 7 - Receive mode impulse diagram............................................................................................ 17 Figure 8 - TxD input circuitry ................................................................................................................. 18 Figure 9 - RxD output circuitry............................................................................................................... 19 Figure 10 - Characteristic of current limitation VCC = f (IVCC) ............................................................... 20 Figure 11 - Reset behaviour .................................................................................................................. 21 Figure 12 - Output current of reset output vs. VCC voltage .................................................................. 21 Figure 13 - EN input circuitry ................................................................................................................. 22 Figure 14 - EN controlled via MCU........................................................................................................ 22 Figure 15 - Permanent normal mode..................................................................................................... 23 Figure 16 - Power dissipation LIN transceiver @ 20kbit ....................................................................... 24 Figure 17 - Save operating area............................................................................................................ 25 Figure 18 - ESR Curves for 6.8F CL 100F and Frequency of 100 kHz ....................................... 26 Figure 19 - Application circuit (slave node) ........................................................................................... 27 Figure 20 - Example circuitry for connection of RxD to MCU for flash programming........................... 28 TH8062 - Datasheet 3901008062 Page 3 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 1. Functional Diagram VSUP Aux. Supply Vaux VCC control amplifier current limitation Reset Generator MR BG VBG Adjust ment SBY Vaux TSHD Temp. Protection SBY MR POR 4.65 V EN VCC 20s Mode Control Osc Reset PORTimer 4/8/15/30ms VBAT_Res VCC VBATReset VSUP Vaux Vaux Wake-up Control RESETBuffer RESET Wake-Filter Receiver VSUP Vaux 70s RxDBuffer VCC Rec-Filter 30k RxD VCC Transmitter SBY BUS GND Driver control 15k Filter MR TxD Figure 1 - Block diagram TH8062 - Datasheet 3901008062 Page 4 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 2. Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings (in accordance with IEC 134) given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Correct operating of the device cannot be guaranteed if any of these limits are exceeded. 2.1 Operating Conditions Parameter Supply voltage Output voltage Operating ambient temperature Junction temperature Symbol VSUP VCC TA TJ Min 6 4.85 -40 Max 18 5.15 +125 +150 Unit V V C C 2.2 Absolute Maximum Ratings Parameter Supply voltage at VSUP Jump start capability Load dump Input voltage at pin BUS Difference VSUP-VCC Input voltage at pin EN Input voltage at pin TxD, RxD, RESET Input current at pin EN, TxD, RxD, RESET Input current for short circuit of pin VSUP and VCC ESD Capability on pin BUS, VBAT, GND ESD Capability on pin TxD, RxD, EN, RESET, VCC Power dissipation Thermal resistance from junction to ambient Junction temperature [2] Storage temperature [1] [2] See chapter 4.1 Safe Operating Area See chapter 3.5 Overtemperature Shutdown Symbol Condition Min -1.0 Max 18 30 40 30 40 40 VSUP+0.3 VCC+0.3 25 500 4 2 Unit VSUP T 300 s T 500ms -24 -0.3 -0.3 -0.3 -25 -500 V VBUS VSUP-VCC VINEN VIN IIN IINSH ESDBUSHB ESDBUSHB P0 RTHJA TJ TSTG T 500ms V V V V mA mA kV kV Human body Model, 100pF via 1.5k Human body Model, 100pF via 1.5k -4 -2 Internal limited [1] 130 150 -55 150 K/W C C TH8062 - Datasheet 3901008062 Page 5 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 2.3 Static Characteristics Unless otherwise specified all values in the following tables are valid for VSUP = 6 to 18V and TAMB = -40 to 125oC. All voltages are referenced to ground (GND), positive currents flow into the IC. 2.3.1. Voltage Regulator and Reset Unit Parameter Symbol Condition VSUP Operating voltage Supply current, VCC noload" VSUP ISnl VSUP = 13V, VEN = VCC , CLOAD=22F, BUS: 1k to VSUP, VSUP = 13V, VEN = 0V, BUS: 1k to VSUP VSUP ramp up VSUP ramp down VSUVR_OFF - VSUVR_ON VCC 6V VSUP 18V 1mA ILOAD 70mA TA = 25C TA = -40C to 125C 18V VSUP 40V ILOAD = 10mA IVCC = 10mA IVCC = 30mA IVCC = 70mA 6V VSUP 18V ILOAD = 1mA ILOAD = 1mA ILOAD = 1mA VSUP > 0V VSUP = 12V, fi = 120Hz, ViP-P = 1V, ILOAD = 10mA VCC ramp up, t > trr 4.4 10mA 30mA 70mA 80 110 t.b.d 4.65 4.8 3.2 2.7 0.2 6 12 150 18 250 V A B A Min Typ Max Unit T[1] Supply current, sleep mode" VSUP under voltage reset "off" threshold VSUP under voltage reset "on" threshold VSUP under voltage reset hysteresis ISsleep VSUVR_OFF VSUVR_ON VSUVR_HYS 15 3.7 3.1 30 4.2 3.5 A V V V A A A A Output voltage VCC VCCn 4.90 4.85 4.80 5.0 5.10 5.15 5.25 V A VCCh VD10 Drop-out voltage [2] VD30 VD70 Line regulation VLNR VLDR10 Load regulation VLDR30 VLDR70 Output current limitation Ripple Rejection on VSUP Reset threshold - POR IVCC_max PSRR VRES(ON) V mV mV mV mV mV mV mV mA dB V A A A A A A A A A 75 220 500 120 350 800 20 50 90 150 140 A TH8062 - Datasheet 3901008062 Page 6 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Parameter Reset threshold - low voltage reset Vres Hysteresis VRESHYS = |VRES(ON) - VRES(OFF)| Master reset threshold Symbol VRES(OFF) VRESHYS VMRES Enable Input EN Input voltage low Input voltage high Hysteresis Pull-down resistor EN low Pull-down current EN high VENL VENH VENHYS RpdENL IpdENH 0V VEN 0.8V VEN VENH Output RESET Output voltage low Pull-up current VOL1_RESET IOUT = 1 mA, VSUP 6 V Ipu Thermal Protection Thermal shutdown Thermal recovery TJSHD TJREC 155 126 180 C C D D -500 -375 0.8 -250 V A A A -0.3 2.0 50 14 0.5 25 2 0.8 VSUP +0.3 300 36 10 V V mV k A B B C A A 3.0 3.15 Condition VCC ramp down, t > trr Min 4.4 Typ 4.65 Max 4.8 150 3.3 Unit T[1] V mV V A C D [1] [2] A = 100% serial test, B = Operating parameter, C = Only used for data characterization (cpk), D = Value guaranteed by design The nominal VCC voltage is measured at VSUP =12V. If the VCC voltage is 100mV below its nominal value then the voltage drop is VD = VSUP - VCC. TH8062 - Datasheet 3901008062 Page 7 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 2.3.2. LIN Bus Interface Parameter Symbol Condition General Pull up current BUS (recessive) Pull up resistor BUS Reverse current BUS (recessive) Reverse current BUS (loss of battery) Reverse current BUS (loss of ground) IINBUSpu RBUSpu VBUS = 18 V, VSUP = 6V VSUP = 12V, VBUS = 0V 20 -1 20 -1 1 30 20 60 A k mA A mA A A A A A Min Typ Max Unit T[1] -IINBUSrev VSUP = 12V, VBUS = 0V IINBUS_lob VSUP = 0V, 0V VBUS 18V IINBUS_log VSUP= 12V, 0V VBUS 18V Receiver Vthr_rec, Vthr_dom Vthr_cnt Vthr_hys Transmitter 7.0 V VSUP 18 V Receive threshold Centre point of receive threshold Vthr_cnt = (Vthr_rec+Vthr_dom)/2 Hysteresis of receive threshold Vthr_hys = Vthr_rec-Vthr_dom 0.4 0.475 0.5 0.15 0.6 0.525 0.175 A VSUP A A Output voltage BUS (dominant) Current limitation BUS VBUSdom_1 ILIM IBUS = 40mA VBUS = VSUP, TxD = 0V Input TxD 41 120 1.2 200 V mA A A Pull-up resistor Input voltage low TxD Input voltage high TxD Rpu_TxD VIL VIH VIN = 0V 9.5 15 23 0.3 k A VCC A VCC A 0.7 Output RxD Output voltage Low RxD Output voltage High RxD VOL VOH IOUT = 1 mA IOUT = -1 mA VCC - 0.8 0.8 V V A A [1] A = 100% serial test, B = Operating parameter, C = only used for data characterization (cpk), D = Value guaranteed by design TH8062 - Datasheet 3901008062 Page 8 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 2.4 Dynamic Characteristics 6V VSUP 18V, -40C TA 125C, unless otherwise specified Parameter Symbol Condition RESET VSUP = 12V,Vers. "A" Reset time tRes VSUP = 12V,Vers. "B" VSUP = 12V,Vers. "C" VSUP = 12V,Vers. "D" Reset rising time trr VSUP = 12V 5.6 2.8 10.5 21 3.0 8 4 15 30 6.5 10.4 5.2 19.5 39 12 ms ms ms ms s A A A A A Min Typ Max Unit T[1] Wake-up and Mode Select Wake up time Debouncing time EN Propagation delay EN to sleep mode Propagation delay EN to normal mode Setup time TxD to EN for low slew mode Hold time TxD after EN for low slew mode twake_BUS tdeb_EN tpd_EN_sleep tpd_EN_norm tset_TxD_LS thold_TxD_LS General LIN Parameter Slew rate rising edge BUS Slew rate falling edge BUS Slew rate rising edge BUS Slew rate falling edge BUS Receiver debouncing time Receiver propagation delay BUS->RxD Symmetry propagation delay BUS->RxD Internal capacity dV/dTrise dV/dTfall dV/dTrise dV/dTfall tdeb_BUS tdr_RxD tdf_RxD tdsym_RxD CBUS CL(RXD) = 50 pF tdr_RXD - tdf_RXD Pulse at BUS via 10kOhm with 0/10 V; VSUP = open -2 25 Normal Mode BUS-Load: 1kOhm/1nF 0.8 -2.5 0.3 -1.3 1.5 1.5 -1.5 0.8 -0.8 2.8 2.5 -0.8 1.3 -0.3 4.0 6 2 35 V/s V/s V/s V/s s s s pF C C C C C A A D 30 2 CLoad = 22F RLoad = 169 Ohm CLoad = 22F RLoad = 169 Ohm 5 20 70 6 150 15 400 400 s s s s s s A D A A B B Low Slew Mode BUS-Load: 1kOhm/1nF TH8062 - Datasheet 3901008062 Page 9 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Parameter Symbol Condition Min Typ Max Unit T[1] LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (20kbit/s) Conditions: Normal slew mode; VSUP =7.0V to 18V; BUS loads: 1k/1nF; 660/6.8nF; 500/10nF TxD signal: tBit = 50s, twH = TwL = tBit; trise = tfall < 100ns trec(min) trec(max) D1 D2 D1 = trec(min) / (2*tBit) D2 = trec(max) / (2*tBit) 40 40 0.396 0.581 50 50 58 58 s s A A Minimal recessive bit time [2] Maximum recessive bit time [2] Duty cycle 1 Duty cycle 2 LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 (10.4kbit/s) Conditions: Low slew mode; VSUP =7.0V to 18V; BUS loads: 1k/1nF; 660/6.8nF; 500/10nF TxD signal: tBit = 96s, twH = TwL = tBit; trise = tfall < 100ns trec(min) trec(max) D1 D2 D1 = trec(min) / (2*tBit) D2 = trec(max) / (2*tBit) 80 80 0.417 0.590 96 96 113 113 s s A A time [2] Minimal recessive bit time [2] Maximum recessive bit Duty cycle 1 Duty cycle 2 LIN transceiver parameter according to SAE J2602 (10.4kbit/s) Conditions: Low slew mode; VSUP =7.0V to 18V; BUS loads: 1k/1nF;660/6.8nF;500/10nF TxD signal: tBit = 96s, twH = TwL = tBit; trise = tfall < 100ns [2] [2] Minimal recessive delay TxD -> BUS Minimal dominant delay TxD -> BUS Maximum rec. to dom. delay Maximum dom. to rec. delay tx_rec_min tx_rec_max tx_dom_min [2] 48 48 48 48 tx_rec_max - tx_dom_min tx_dom_max - tx_rec_min 15.9 17.2 s s s s s s A A Maximum recessive delay TxD -> BUS [2] Maximum dominant delay TxD -> BUS tx_dom_max Tr_d_max Td_r_max [1] [2] A = 100% serial test, B = Operating parameter, C = only used for data characterization (cpk), D = Value guaranteed by design See chapter 2.5 Timing Diagrams TH8062 - Datasheet 3901008062 Page 10 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 2.5 Timing Diagrams 50% TxD tdf_TXD VBUS 100% 95% tdr_TXD BUS 50% 50% 5% 0% tdf_RXD tdr_RXD RxD 50% Figure 2 - Timing diagram for propagation delays tBit tBit TxD tx_dom_max tx_dom_min VSUP 100% tx_rec_max tx_rec_min tdom(max) tdom(min) 74.4% (77.8%) trec(min) BUS 58.1% (61.6%) 28.4% (25.1%) 42.2% (38.9%) 58.1% (61.6%) 28.4% (25.1%) trec(max) VSS 0% Remark: The levels for low slope mode are shown in brackets Figure 3 - Timing diagram for duty cycle acc. to LIN 2.0 and J2602 TH8062 - Datasheet 3901008062 Page 11 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Normal Mode Sleep Mode Normal Mode Ini-Phase Low Slew tpdEN_sleep 5V 4.5V VCC 0.5V 0V tpdEN_norm tset_TxD_LS EN 0.8V 2.0V 2V thold_TxD_LS TxD 50% Figure 4 - Timing Diagram for EN mode selection TH8062 - Datasheet 3901008062 Page 12 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3. Functional Description The TH8062 consists of a low drop voltage regulator 5V/70mA and a LIN bus transceiver, which is a bidirectional bus interface for data transfer between LIN bus and the LIN protocol controller. Additionally integrated is a RESET unit with a fixed power-on-reset delay of 8ms (optional 4,15 or 30ms). 3.1 Operating Modes The TH8062 provides three main operating modes "normal", "sleep" and "low slew" and the intermediate states "Ini-state" and "thermal shutdown". The main modes are fixed states defined by basic actions (VSUP start, EN or wake-up). The intermediate states are soft states. They aren't defined by logical actions but by changes of voltage (VSUP, VCC) or junction temperature. VSUP power on Set Slew_State = L UVR / POR VSUP > UVR_OFF clear Reset-Timer Start Regulator -> VCC ramp up RESET = L Wake-up disabled VCC > Vres (4.65V) & Slew_State=L Regulator on RESET = L / after tres RESET=H Wake-up disabled LIN-Transceiver on/ normal slew mode VSUP < UVR_ON EN= L/H edge & TxD=H Ini-state VCC < Vres NormalMode Tj > Tjshd Tj < Tjrec Tj > Tjshd VSUP < UVR_ON VCC > Vres (4.65V) & Slew_State=H VSUP > UVR_ON & BUS Wake-up) EN= L/H edge & TxD=L thermal shutdown Tj > Tjshd VCC < Vres EN= H/L Regulator off Wake-up disabled LIN-Transceiver off EN=L SleepMode EN= H/L Regulator off Thermal shutdown off Wake-up enabled (LIN-Receiver on) LIN-Transmitter off Low Slew Mode Regulator on RESET = L / after tres RESET=H Wake-up disabled Set Slew State = H LIN-Transceiver on/ low slew mode Figure 5 - State diagram of operating modes TH8062 - Datasheet 3901008062 Page 13 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Normal Mode This mode is the base mode. The bus transceiver is able to send with a max baud rate of 20kbit/s. The whole TH8062 is active. Switching to normal mode can be done via the following actions: - Start of VSUP or after under voltage reset - Rising edge at EN (EN=high) and TxD=high (local wake-up) - Activity on the LIN bus (remote wake-up) Sleep Mode Sleep mode is most current saving. With a falling edge on EN (EN=low) the TH8062 is switched from normal mode into sleep mode. The voltage regulator and the reset unit will be switched off and the LIN transceiver is in recessive state. Switching into sleep mode can be done independently from the current transceiver state. That means if the transmitter is in dominant state this state will be cancelled and it will be switched to recessive state. Low Slew Mode In this mode the slew rate is switched from the normal value of typ. 1.6V/s to a low value of typ. 0.8V/s. This mode is optimized to send with a maximum baud rate of 10.4kbit/s (SAE J2602). Because of this reduction of the slew rate the EME behaviour is improved especially in the frequency range of 100 kHz to 10MHz. Switching to this mode is possible with a combination of rising edge on EN together with a low level on TxD. The IC operates in this mode until the next under voltage reset occurs. POR-state This is the power-on-reset state of the TH8062, while Vsup < VSUVR_OFF. If the prior state was sleep mode, the TH8062 switches via the ini-state to normal mode. Ini-state This is an intermediate state, which will pass through after switch on of VSUP or VCC. The TH8062 remains in this state if VCC is below VRES (Reset output = L) and Vsup > VSUVR_ON. Thermal Shutdown If the junction temperature TJ is higher than TJSHD (>155C), the TH8062 will be switched into the thermal shutdown mode. The behaviour within this mode is comparable with the sleep mode except for LIN transceiver operating. The transceiver is completely disabled; no wake-up functionality is available. If TJ falls below the thermal recovery temperature TJREC (typ. 140C) the TH8062 will be recover to the previous state (normal, sleep or low slew). TH8062 - Datasheet 3901008062 Page 14 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.2 Initialization Initialization starts when the power supply is switched on as well as every rising edge on of the TH8062 via the EN pin. VSUP- Power-ON If VSUP is switched on the TH8062 starts to normal mode via the POR- and Ini-state. A combination of dynamic POR and under voltage reset circuitry generates a POR signal, which switches the TH8062 into normal mode. This power on behaviour is independent from the status of the EN-pin. Power-on reset and under-voltage reset operate independent from each other, which secures the independence from the rise time of VSUP. During fast VSUP edges the power-on reset will be active. If the increasing of VSUP is very slow (> 1ms/V) and VSUP > VSUVR_OFF (typ. 4.2V) the under voltage reset unit initializes the voltage regulator. The effects of both POR circuits at different VSUP slopes will show in Figure 6. VSUP VSUVR_OFF VSUVR_ON UVR POR EN=H/L POR UVR VCC normal mode sleep mode normal mode Figure 6 - Operating of power-on and under-voltage reset After POR the voltage regulator starts and the VCC voltage will be output. If VCC>VMRes the bus interface will be activated. If the VCC voltage level is higher than VRES, the reset time tRes is started. After tRes the RESET output switches from low to high (see Figure 11). The Initialization procedure operates after POR independent from the EN voltage. Start of Linear Regulator via Wake-up The initialization is only being done for the VCC circuitry parts. This procedure begins with leaving the master reset state (VCC > VMRes) and runs in the same manner as the VSUP-Power-On. 3.3 Wake-Up If the regulator is put into sleep mode it can be woken up with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of min. 70s switches on the regulator. The low slew mode has to be selected again if necessary. After the BUS has woken up the regulator, it can only be switched off with a high level followed by a low level on the EN pin. TH8062 - Datasheet 3901008062 Page 15 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.4 VSUP under voltage reset The under voltage detection unit inhibits an undefined behaviour of the TH8062 under low voltage condition (VSUP < 4V). If VSUP drops below VSUVR_ON (typ. 3.1V) the under voltage detection becomes active and the IC will be switched to POR state. The following increasing of VSUP above VSUVR_OFF (typ. 3.7V) cancels this POR state and the voltage regulator starts with the initialization sequence. VSUP under voltage in Normal Mode Supply Voltages below VSUVR_OFF do not influence the voltage regulator. The output voltage Vcc follows VSUP. VSUP under voltage in Sleep Mode No exit from the sleep mode will take place if the VSUP voltage drops down to VSUVR_ON (typ. 3.5V). The under voltage reset becomes active (POR-state) if the voltage drops below 2.7V. As a result of this functioning, the sleep mode is left to the normal mode. If VSUP rises again above VSUVR_OFF (typ. 4.2V) the IC initializes the voltage regulator and continues to work with the normal mode. The under voltage reset unit secures stable functioning in the under voltage range of VSUP down to GND level. The dynamic Power-On-Reset secures a defined internal state independent from the duration of the VSUP drop, which guarantees a stable restart. VSUP under voltage in Low Slew Mode The behaviour of TH8062 at low VSUP voltages is equal to the sleep mode. The low slew mode will be cancelled, if VSUP drops below VSUVR_ON in this mode. The TH8062 enters the normal mode, if VSUP rises again above VSUVR_OFF. 3.5 Overtemperature Shutdown If the junction temperature is 155C < TJ < 175C the over-temperature recognition will be activated and the regulator voltage will be switched off. The VCC voltage drops down, the reset state is entered and the bustransceiver is switched off (recessive state). After TJ falls below 140C the TH8062 will be initialized again (see Figure 11). This initialisation starts independently from the voltage levels on EN and BUS. Within the thermal shutdown mode the transceiver can not switch to the normal mode neither with local nor with remote wake-up. The operation of the TH8062 is possible between TAmax (125C) and the switch off temperature, but small parameter differences can appear. After over-temperature switch-off the IC behaves as described in chapter 3.8 RESET. TH8062 - Datasheet 3901008062 Page 16 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.6 LIN BUS Transceiver The TH8062 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a debouncing unit. Transmit Mode During transmission the data at the pin TxD will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit. Transmitting will be interrupted in the following cases: - Sleep mode - Thermal Shutdown active - Master Reset (VCC < 3.15V) The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the TH8062 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k resistor in series with a diode to VBAT. Receive Mode The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus signal are suppressed by the implemented debouncing circuit ( = 2.8s). VSUP Vthr_max 60% BUS 50% 40% Vthr_hys Vthr_min Vthr_cnt t < tdeb_BUS t < tdeb_BUS RxD Figure 7 - Receive mode impulse diagram The receive threshold values Vthr_max and Vthr_min are symmetrical to the centre voltage of 0.5*VSUP with a hysteresis of 0.175*VSUP. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed. TH8062 - Datasheet 3901008062 Page 17 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Slew Modes and Data rates The TH8062 is a constant slew rate transceiver which means that the bus driver works with a mode depended slew rate. In normal mode the slew rate is typical 1.6 V/s (max. baudrate 20kbit/s) and in low slew mode typical 0.8 V/s. The lower slew rate in low slew mode associated with a baud rate of 10.4kbit/s improves the EME behaviour. The LIN transceiver of TH8062 is compatible to the physical layer specification according to LIN 2.0 specification for data rates up to 20kbit/s and the SAE specification J2602 for data rates up to 10.4kbit/s. The constant slew rate principle is very robust against voltage drops and can operate with RC- oscillator systems with a clock tolerance up to 2% between 2 nodes. Low Slew Mode In this mode the slew rate is switched from the normal value of typ. 1.6V/s to a low value of typ. 0.8V/s. This mode is optimized to send with a maximum baud rate of 10.4kbit/s (acc. to SAE J2602). Because of this reduction of the slew rate the EME behaviour is improved especially in the frequency range of 100 kHz to 10MHz. Input TxD The 5V input TxD controls directly the BUS level: TxD = low TxD = high -> -> BUS = low (dominant level) BUS = high (recessive level) The TxD pin has an internal pull up resistor connected to VCC. This guarantees that an open TxD pin generates a recessive BUS level. MCU VCC RPU_TXD VCC Typ. 15k TH8062 IPU_TXD RC-Filter (10ns) TxD Figure 8 - TxD input circuitry TH8062 - Datasheet 3901008062 Page 18 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Output RxD The received BUS signal will be output to the RxD pin: BUS < Vthr_cnt - 0.5 * Vthr_hys BUS > Vthr_cnt + 0.5 * Vthr_hys -> -> RxD = low RxD = high This output is a push-pull driver between VCC and GND with an output current of 1mA. TH8062 VCC RxD MCU Figure 9 - RxD output circuitry TH8062 - Datasheet 3901008062 Page 19 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.7 Linear Regulator The TH8062 has an integrated low drop linear regulator with a p-channel-MOSFET as driving transistor. This regulator outputs a voltage of 5V 3% and a current of 70mA within an input voltage range of 6V VSUP 18V. The current limitation unit limits the output current for short circuits or overload to 130mA respectively drop-down of the VCC voltage. 6 5 VCC [V] 4 3 2 1 0 0 20 40 60 80 100 120 140 Iload [mA] Figure 10 - Characteristic of current limitation VCC = f (IVCC) TH8062 - Datasheet 3901008062 Page 20 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.8 RESET The TH8062 contains a reset unit which secures the correct initialization and generation of the reset signal. The RESET pin outputs the reset state of the TH8062. The POR timer will be started if VSUP is switched on and VCC> POR threshold. After the time tRes the RESET output is switched from low to high. The RESET unit combines a VCC low voltage detection unit with fixed POR timer This output is switched from low to high if VSUP is switched on and VCC>VRES after the time tRes . All conditions which cause a drop of the VCC voltage will be detected from the low voltage reset unit which generates a reset signal. The TH8062 will be reinitialized if the VCC voltage rises above the low voltage limit. If the voltage VCC drops below VRES then the RESET output is switched from high to low after the time trr has been reached. For this reason short breaks of the VCC voltage and uncontrolled reset generations will be inhibited. The circuitry of the RESET output driver guarantees, that the reset low level during decreasing of the VCC voltage will be kept secure (see Figure 12). VSUP T>Tj T VRES tRes trr tRes t tRes RESET Initialisation Thermal shutdown Spike VSUP Current limitation Low voltage active VSUP Spike VCC Figure 11 - Reset behaviour Figure 12 - Output current of reset output vs. VCC voltage 3.8.1. Programmability of Power-ON-Reset Delay The standard POR time of the TH8062 is typ. 8ms. During final test it is possible to re-program this time to other values. Possible values are 4ms, 15ms and 30ms. See ordering code for details. TH8062 - Datasheet 3901008062 Page 21 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 3.9 Mode Input EN The TH8062 is switched into the sleep mode with a falling edge and into normal mode with a rising edge at the EN pin. The normal mode will be kept as long as EN = high. The deactivation of TH8062 with a falling edge at EN can be done independently from the state of the bustransceiver. EN 23k voltage limiter Filter 6s 1.5M enable ESD Figure 13 - EN input circuitry The maximum input voltage is VSUP. The threshold is typ. 1.4V and therefore also 5V and 3.3V CMOS levels can be used as input signal. Figure 13 shows the internal circuitry of the EN pin. The EN input has an internal pull down resistor of typ. 25k to secure that if this pin is not connected a low level will be generated. An input debouncing filter of 6s suppresses effectively disturbance couplings via the EN pin It will use different pull down resistors for normal and sleep mode to minimize the sleep mode current. The wide input voltage range allows different EN control possibilities. If the EN input is connected to a CMOS output of the MCU, a falling edge switches the TH8062 into sleep mode (the regulator is also switched off). The wake up is only possible via the bus line. TH8062 VBAT CIN LIN 180p VSUP EN GND BUS VCC RESET TxD RxD Cload MCU +5V Figure 14 - EN controlled via MCU TH8062 - Datasheet 3901008062 Page 22 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver If the application doesn't need the wake up capability of the TH8062 a direct connection EN to VSUP is possible. In this case the TH8062 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via a VBAT signal. If this is a direct VBAT signal an external reverse battery protection has to be added to the circuitry. TH8062 VBAT CIN LIN 180p 10k VSUP EN GND BUS VCC RESET TxD RxD Cload MCU +5V Figure 15 - Permanent normal mode TH8062 - Datasheet 3901008062 Page 23 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 4. Application Hints 4.1 Safe Operating Area The maximum power dissipation depends on the thermal resistance of the package and the PCB, the temperature difference between Junction and Ambient as well as the airflow. The power dissipation can be calculated with: PD = (VSUP - VCC) * IVCC + PD_TX The power dissipation of the transmitter PD_TX depends on the transceiver configuration and its parameters as well as on the bus voltage VBUS=VBAT-VD, the resulting termination resistance RL, the capacitive bus load CL and the bit rate. Figure 16 shows the dependence of power dissipation of the transmitter as function of VSUP. The conditions for calculation of the power dissipation is RL=500, CL=10nF, bit rate=20kbit and duty cycle on TxD of 50% 50 45 40 35 PD [mW] 30 25 20 15 10 5 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VSUP [V] Figure 16 - Power dissipation LIN transceiver @ 20kbit The permitted package power dissipation can be calculated: PDmax = T j - TA RTHJ - A If we consider that PD_TX_max= f (VSUP) the max output current IVCC on VCC can be calculated: T j - TA I VCCmax = RTHJ - A - PD _ TX _ max @ VSUP VSUP - VCC TJ -TA is the temperature difference between junction and ambient and Rth is the thermal resistance of the package. The thermal energy is transferred via the package and the pins to the ambient. This transfer can be improved with additional ground areas on the PCB as well as ground areas under the IC. TH8062 - Datasheet 3901008062 Page 24 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 80 70 60 IVCC_max [mA] max. supply voltage maximum current 50 40 30 20 10 0 5 6 7 8 9 10 11 12 SOIC8 TA=125C SOIC8 TA=85C MLPD TA=125C 13 14 15 16 17 18 19 VSUP [V] Figure 17 - Save operating area The linear regulator of the TH8062 operates with input voltages up to 18V and can output a current of 70mA. The maximum power dissipation limits the maximum output current at high input voltages and high ambient temperatures. The output current of 70mA at an ambient temperature of TA = 125C is only possible with small voltage differences between VSUP and VCC. See Figure 17 for safe operating areas for different ambient temperatures. 4.2 Low Dropout Regulator The voltage regulator of theTH8062 is a low dropout regulator (LDO) with a p-MOSFET as driving transistor. This kind of regulator has a standard pole, generated from the internal frequency compensation and an additional pole, which is dependent from the load and the load capacitance. This additional pole can cause an instable behaviour of the regulator! It is required a zero point to compensate this additional pole. It can be realised via an additional load resistor in series with a load capacitor. It is used for this compensation the equivalent series resistance (ESR) of the load capacitor. Every real capacitor is characterized with an ESR value. With the help of this ESR value an additional zero point is implemented into the amplification loop and therefore the result of the negative phase shift is compensated. Because of this correlation the regulator has a stable operating area which is defined by the load resistance RL, the load capacitor CL and the corresponding ESR value. The load resistance resp. load current is defined by the application itself and therefore the compensation of the pole can only be done via variation of the load capacitance and ESR value. Input Capacitor on VSUP CIN An input capacitance of CIN 4.7F is necessary. Higher capacitance values improve the line transient response and the supply noise rejection behaviour. The combination of electrolytic capacitor (e.g.100F) in parallel with a ceramic RF-capacitor (e.g.100nF) archives good disturbance suppressing. The input capacitor should be placed as close as possible (< 1cm) to the VSUP pin. TH8062 - Datasheet 3901008062 Page 25 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Load Capacitor on VCC CL The regulator is stabilized by the output capacitor CL. The TH8062 requires a minimum of 4.7F capacitor connected to the 5V output to insure stability. This capacitor should maintain its ESR in the stable region of the ESR curve (See Figure 18) over the full operating temperature range of the application. It has to be taken into account that the capacitance value and the ESR of a capacitor changes with temperature. The minimal capacitance value must also be kept within the whole operating temperature range. 100 ESR@100kHz [Ohm] 10 1 Stable Area 0,1 0,01 0 10 20 30 40 50 load current [mA] Figure 18 - ESR Curves for 6.8F CL 100F and Frequency of 100 kHz The value and type of the output capacitor can be selected using the diagram shown in Figure 18. The load capacitor should be placed as close as possible (< 1cm) to the VCC pin. Capacitance Value The capacitance value of an electrolytic capacitor depends on the voltage, temperature and the frequency. The temperature coefficient of the capacitor value is positive, that means that the value increases with increasing of the temperature. The capacitance value decreases with increasing of the frequency. This behaviour of a capacitor can cause that at TA=-40C the capacitance value falls below the minimum required capacitance for the regulator. In this case the regulator becomes instable, which means the regulator starts oscillation. The nominal value of the capacitor at TA=25C has to be chosen with enough margin under consideration of the capacitor specification. The instable behaviour will be amplified because of the decreasing of the capacitance with this oscillation. ESR The equivalent serial resistance is the resistor part of the equivalent circuit diagram of a capacitor. The ESR value depends on the temperature and frequency. Normally the specified ESR values for a capacitor is valid at a temperature of TA=25C and a frequency of f=100 kHz. The temperature coefficient is negative, which means with increasing of the temperature the ESR value decreases. When choosing the capacitance, it has to take into account that the ESR can decrease at TA=40C dramatically that the valid operating area can be left, which causes that the regulator will be instable. TH8062 - Datasheet 3901008062 Page 26 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver Tantalum Capacitors This type of capacitor has a low dependence of the capacitance and the ESR from the temperature and is therefore well suitable as VCC load capacitor. Aluminium Capacitors These capacitors show a strong influence of the capacitance and the ESR from the temperature. These characteristic restrains the usability as load capacitor for the low drop regulator of TH8062. 4.3 Application Circuitry TH8062 VBAT CIN LIN 10 180p Optional ESD Protection Cload VCC MCU +5V VSUP EN GND BUS RESET TxD RxD Figure 19 - Application circuit (slave node) 4.4 EMI Supressing To minimize the influence of EMI on the bus line a 180pF capacitor should be connected directly to the BUS pin (see Figure 19). This EMI-Filter makes sure that the RF injection into the IC from the BUS line have no affect resp. will be limited. Alternatively to a pure C-filter it is also possible to use LC- or RC-filter. The dimension of C, L or R, L depends on the corner frequency, the maximum LIN bus capacitance (10nF) and the compliance with the DC- and AC LIN bus parameters. TH8062 - Datasheet 3901008062 Page 27 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 4.5 Connection to Flash-MCU While programming a flash MCU the TH8062 should be disconnected from the MCU. This can be done by disconnecting the supply voltage from the TH8062 or by switching off with the EN pin. The reverse current supply of the IC via the RxD pin, if the connected MCU pin is used as normal signal input and programming input, must be inhibited via a decoupling diode. In this case the MCU must be supplied via the programming interface. Prog.-Data 10u...47u TH8062 VCC RESET TxD RxD Vhigh_RxD >= 4.7V at VCC = 5V Vlow_RxD = 0.8V 0.7V 47n...100n MCU Vhigh = 4V at VCC = 5V Figure 20 - Example circuitry for connection of RxD to MCU for flash programming The programming of the Flash is also possible via the LIN pin, if the MCU supports this kind of flash mode. TH8062 - Datasheet 3901008062 Page 28 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 5. Operating during Disturbance 5.1 Operating without VSUP or GND The absence of VSUP or GND connection will not influence or disturb the communication between other bus nodes. No reverse supply of the IC can appear if without GND or VSUP connection the BUS pin is on VBAT level. 5.2 Short Circuit BUS against VBAT The reaction of the IC depends on the send state of the transceiver: - Recessive LIN bus is blocked, no influence to the TH8062 - Dominant Current limitation, thermal shut down of TH8062 if power dissipation will make an overrun of TJ 5.3 Short Circuit BUS against GND LIN bus is blocked. No influence on the TH8062. 5.4 Short Circuit TxD against GND The LIN transceiver is permanently in the dominant state, which means the whole LIN bus. This state can only be detected from the LIN controller. In this case the controller must switch off the LIN node via the EN input of the TH8062. A thermal shut down of TH8062 will appear if the power dissipation will make an overrun of TJ. 5.5 TxD open The internal pull-up resistor forces the LIN node to the recessive state. The communication between the other bus-nodes will not be disturbed. 5.6 Short Circuit VCC against GND The VCC pin is protected via a current limitation. This state is comparable with the behaviour in the sleep mode. 5.7 Overload of VCC Thermal switch off The power dissipation is increasing if the load current is between IVCC_max and ILVCC. If the max junction temperature of >155C is reached, the IC will be switched off. The voltage regulator will also be switched off and a reset signal is forced. Over current If the current limitation is active the voltage on VCC drops down. If this voltage under-runs the threshold VRES, a reset will be forced. 5.8 Undervoltage VCC The reset unit ensures the correct behaviour of the driver during under-voltage. The BUS pin generates the recessive state if VCC < VMRes (3.15V). The inputs EN and TxD have pull-up or pull-down characteristics. If VCC VMRes the TxD signal is transmitted to the bus. The receive mode is also active. TH8062 - Datasheet 3901008062 Page 29 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 5.9 Undervoltage VSUP The combination of dynamic power on reset and low voltage reset guarantees a defined start up behaviour. If the supply voltage VSUP drops below 3V the low voltage detection becomes active. If the VSUP voltage rises again above 3.5V the low voltage reset will be terminated and the 5V voltage regulator will be started. 5.10 Short circuit RxD, RESET against GND or VCC Both outputs are short circuit proof to VCC and ground. TH8062 - Datasheet 3901008062 Page 30 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 6. PIN Description VSUP EN GND BUS 1 8 VCC RESET TxD RxD 2 3 TH8062 SOIC8 7 6 4 5 Pin 1 2 3 4 5 6 7 8 Name VSUP EN GND BUS RxD TxD RESET VCC IO-Typ P I P I/O O I O O Supply voltage Description Enable input voltage regulator, HV-pull-down-input, High-active Ground LIN bus line Receive output, 5V-push-pull 5V-Transmit input, pull-up-input Reset 5V-output, active low Regulator output 5V/70mA TH8062 - Datasheet 3901008062 Page 31 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 7. Mechanical Specification SOIC8 Small Outline Integrated Circiut (SOIC), SOIC 8, 150 mil A1 B C D E e H h L A 0 8 0 8 ZD A2 All Dimension in mm, coplanarity < 0.1 mm min max min max 0.10 0.25 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 0.150 0.157 1.27 5.80 6.20 0.25 0.50 0.41 1.27 0.016 0.050 1.52 1.72 0.060 0.068 0.53 1.37 1.57 0.054 0.062 All Dimension in inch, coplanarity < 0.004" 0.004 0.014 0.0075 0.189 0.0098 0.018 0.0098 0.196 0.050 0.2284 0.0099 0.244 0.0198 0.021 TH8062 - Datasheet 3901008062 Page 32 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 8. Tape and Reel Specification 8.1 Tape Specification max. 10 max. 10 IC pocket R n. mi Top View Sectional View T2 D0 T G1 K0 B1 S1 G2 T1 Cover Tape P1 B0 P0 P2 E < A0 > F W D1 Abwickelrichtung Standard Reel with diameter of 13" Package SOIC8 D0 1.5 +0.1 E 1.75 0.1 P0 4.0 0.1 P2 2.0 0.05 Tmax 0.6 Parts per Reel 2500 T1 max 0.1 G1 min 0.75 G2 min 0.75 B1 max 8.2 Width 12 mm D1 min 1.5 F 5.5 0.05 P1 4.0 0.1 Rmin 30 Pitch 8 mm T2 max 6.5 W 12.0 0.3 A0, B0, K0 can be calculated with package specification. Cover Tape width 9.2 mm. TH8062 - Datasheet 3901008062 Page 33 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 8.2 Reel Specification W2 W1 B* D* A C N Amax 330 Width of half reel 4 mm 8 mm B* 2.0 0.5 Nmin 100,0 100,0 C 13.0 +0,5/-0,2 W1 4,4 8,4 D*min 20.2 W2 max 7,1 11,1 TH8062 - Datasheet 3901008062 Page 34 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 9. ESD/EMC Remarks 9.1 General Remarks Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 9.2 ESD-Test The TH8062 is tested according CDF-AEC-Q100-002 / MIL883-3015.7 (human body model). 9.3 EMC The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for dataand signal pins. TH8062 - Datasheet 3901008062 Page 35 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 10. Revision History Version 001 002 Update block diagram Update Static Characteristics o Output current limitation o POR Reset time Update Dynamic Characteristics o Add general LIN Parameter Update Assembly Information Changes Remark 1st Release Date April 2005 March 2006 TH8062 - Datasheet 3901008062 Page 36 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 11. Assembly Information Standard information regarding manufacturability of Melexis products with different soldering processes Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity level according to following test methods: Reflow Soldering SMD's (Surface Mount Devices) * * IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A113 Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2) Wave Soldering SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * * EN60749-20 Resistance of plastic- encapsulated SMD's to combined effect of moisture and soldering heat EIA/JEDEC JESD22-B106 and EN60749-15 Resistance to soldering temperature for through-hole mounted devices Iron Soldering THD's (Through Hole Devices) * EN60749-15 Resistance to soldering temperature for through-hole mounted devices Solderability SMD's (Surface Mount Devices) and THD's (Through Hole Devices) * EIA/JEDEC JESD22-B102 and EN60749-21 Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD's is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the Use of Certain Hazardous Substances) please visit the quality page on our website: http://www.melexis.com/quality_leadfree.asp TH8062 - Datasheet 3901008062 Page 37 of 38 March 2006 Rev 002 TH8062 Voltage Regulator with LIN Transceiver 12. Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis' rendering of technical or other services. (c) 2002 Melexis NV. All rights reserved. For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: Phone: +32 1367 0495 E-mail: sales_europe@melexis.com All other locations: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com ISO/TS16949 and ISO14001 Certified TH8062 - Datasheet 3901008062 Page 38 of 38 March 2006 Rev 002 |
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